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Microprocesador 486 . 169 pines - 17x17 Pin arreglo en grilla.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
|-------------------------------------------------------------------|
S | o o o o o o o o o o o o o o o o o |
| |
R | o o o o o o o o o o o o o o o o o |
| |
Q | o o o o o o o o o o o o o o o o o |
| ----------------------------------- |
P | o o o / o o o |
| / |
N | o o o | | o o o |
| | | |
M | o o o | | o o o |
| | | |
L | o o o | | o o o |
| | | |
K | o o o | | o o o |
| | BOTTOM VIEW | |
J | o o o | (pin side) | o o o |
| | | |
H | o o o | | o o o |
| | | |
G | o o o | | o o o |
| | | |
F | o o o | | o o o |
| | | |
E | o o o | | o o o |
| / |
D | o o o o / o o o |
| ----------------------------------- |
C | o o o o o o o o o o o o o o o o o |
| |
B | o o o o o o o o o o o o o o o o o |
| |
A o o o o o o o o o o o o o o o o o |
------------------------------------------------------------------|
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
| PIN | Funcion |
| A2 - A31 | Direccion pins. |
| A20M# | Direccion bit 20 Mascara pin. |
| ADS# | Direccion estatus. |
| AHOLD | Direccion parada. |
| BE0 - BE3# | Byte activar pins. |
| BLAST# | Burst Ultimo. |
| BOFF# | Retorno Entrada. |
| BRDY# | Burst Listo. |
| BRDYC# | Cache Burst Listo. |
| BREQ | Bus Requerimiento. |
| BS8# | Bus Tamaño 8. |
| BS16# | Bus Tamaño 16. |
| CACHE# | Cache. |
| CLK | Reloj Entrada Provee tiempo fundamental para el procesador. |
| CLKMUL | Clock Multiplier pin (Bus Frecuencia). Usualmente 2.0x or 3.0x, though it can be 2.5x or 4.0x, depending on the chip. |
| D0 - D31 | Data pins. |
| D/C# | Data/Codigo. Primario bus cycle definicion pin. |
| DP0 - DP3 | Data Paridad pins. |
| EADS# | External Direccion Strobe. |
| FERR# | Coma Flotante Error. |
| FLUSH# | Cache Flush. |
| HITM# | Hit to a Modificar linea. |
| HLDA | Para comprendida. |
| HOLD | Bus Parada requerimiento. |
| IGNNE# | Ignorar Numero de Error. |
| INTR | Mascara habilitada Interruptor. |
| INV | Invalido. |
| INVAL | Invalido. |
| KEN# | Cache Habilitada. |
| KEY | Key pin. Non-functional pin a prevenir incorrecto CPU insercion. |
| LOCK# | Bus Asegurado. |
| M/IO# | Memoria/Input-Output. Primaria bus ciclo definicion pin. |
| MP# | Math-coprocessor Presente. Cuando es bajada la tension, el procesador entra en bajada de fuente tri estado modo, permitiendo que el math-coprocessor tomar control. |
| NMI | Non-Mascara habilitada Interruptor. |
| PCD | Pagina Cache Disabilitada. |
| PCHK# | Paridad Estatus. |
| PLOCK# | Pseudo-Asegurado. |
| PWT | Pagigina Escrita-Through. |
| RDY# | No-burst Listo. |
| RESET | Reset. |
| RPLSET0 | ?. |
| RPLSET1 | ?. |
| RPLVAL# | ?. |
| SMADS# | Sistema de Manejo Interruptor Direccion Strobe. |
| SMI# | Sistema de Manejo Interruptor Permite al prcesador entrar en un modo de manejo.. |
| SMIACT# | Sistema Management Interrupt Activo. Indica que el procesaro esta en el sistema |
| SRESET | Soft Reset. |
| STPCLK# | Parada Reloj. |
| SUSP# | Suspendido. Mismo que STPCLK#. |
| SUSPA# | ?. |
| TCK | Prueba Reloj. |
| TDI | Prueba Data Input. |
| TDO | Prueba Data Output. |
| TEST | Prueba pin. |
| TMS | Prueba Modo Seleccionado. |
| UP# | Actualizacion presente. Cuando la tension es baja, el procesador entra en poder bajo tri modo estado, permitiendo que la actualizacion tome el control.. |
| VOLDET | Voltage Detectado. |
| WB/WT# | Escribir-Back / Escribir-Through. |
| WM_RST | Warm Reset. |
| W/R | Escribir / Leer. |
Microprocessor 586 - 321 pins - 19x19 (37x37) Staggered Pin Grid Array. Only the AMD K6 has this feature.
CORE voltage | I/O voltage
plane (Vcc2) | plane (Vcc3)
|
1 3 5 7 9 11 13 15 17 19 |21 23 25 27 29 31 33 35 37
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36
|----------------------------------------|----------------------------------|
AN | o o o o o o o o o o |o o o o o o o o o | AN
AM | o o o o o o o o o o| o o o o o o o o | AM
AL | o o o o o o o o o o__|o o o o o o o o o | AL
AK | o o o o o o o o o| o o o o o o o o o | AK
AJ | o o o o o o o o o |o o o o o o o o o o | AJ
AH | o o ---------------------|----------------------- x o o | AH
AG | o o o / | o o o | AG
AF | o o / | o o | AF
AE | o o o | | | o o o | AE
AD | o o | | | o o | AD
AC | o o o | | | o o o | AC
AB | o o | | | o o | AB
AA | o o o | | | o o o | AA
Z | o o | | | o o | Z
Y | o o o | | | o o o | Y
X | o o | | | o o | X
W | o o o | | | o o o | W
V | o o | BOTTOM VIEW | o o | V
U | o o o | (pin side) | o o o | U
T | o o | | | o o | T
S | o o o | | | o o o | S
R | o o | | | o o | R
Q | o o o | | | o o o | Q
P | o o | | | o o | P
N | o o o | | | o o o | N
M | o o | | | o o | M
L | o o o | | | o o o | L
K | o o | | | o o | K
J | o o o | | | o o o | J
H | o o | / o o | H
G | o o o | / o o o | G
F | o o o ---------------------|----------------------- o o | F
E | o o o o o o o o o |o o o o o o o o o o | E
D | o o o o o o o o o| o o o o o o o o o | D
C | o o o o o o o o o |o o o o o o o o o o | C
B | o o o o o o o o o| o o o o o o o o o | B
A o o o o o o o o |o o o o o o o o o o | A
----------------------------------|--------------------------------------|
1 3 5 7 9 11 13 15 17 |19 21 23 25 27 29 31 33 35 37
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36
|
CORE voltage | I/O voltage
plane (Vcc2) | plane (Vcc3)
Common Pin Designations
| A3 - A31 | Address pins. |
| A20M# | Address bit 20 Mask pin. |
| ADS# | Address Status. |
| ADSC# | Cache Address Strobe. Functionally the same as ADS#. |
| AP | Address Parity. |
| APCHK# | Address Parity Check. |
| BE0# - BE7# | Byte Enable pins. |
| BF0 - BF2 | Bus Frequency clock multiplier (bus to core frequency ratio). 1.5x and 2.0x when only BF0 is present. 1.5x, 2.0x, 2.5x, and 3.0x when BF0 and BF1 are present. 2.0x, 2.5x, 3.0x, 3.5x, 4.0x, 4.5x, 5.0x, and 5.5x when BF0, BF1, and BF2 are present. [ Note: What multipliers are available is entirely dependent on the processor itself. ] |
| BOFF# | Back off input. |
| BRDY# | Burst Ready. |
| BRDYC# | Cache Burst Ready. Functionally the same as BRDY#. |
| BREQ | Bus Request. |
| BUSCHK# | Bus Check. |
| CACHE# | Cache. |
| CLK | Clock input. Provides fundamental timing for the processor. |
| D/C# | Data/Code. Primary bus cycle definition pin. |
| D0 - D63 | Data pins. |
| DP0 - DP7 | Data Parity pins. |
| EADS# | External Address. |
| EWBE# | External Write Buffer Empty. |
| FERR# | Floating Point Error. |
| FLUSH# | Cache flush. |
| HIT# | Hit. Reflects the outcome of an inquire cycle. |
| HITM# | Hit to a Modified line. Reflects outcome of an inquire cycle. |
| HLDA | Bus Hold Acknowledge. |
| HOLD | Bus Hold request. |
| IERR# | Internal Error. Indicates parity or functional redundancy errors. |
| IGNNE# | Ignore Numeric Error. |
| INIT | Processor Initialization pin. |
| INTR/LINT0 | Active mask able Interrupt. If APIC is enabled, this becomes LINT0. |
| INV | Invalidation. Determines final cache line state. |
| KEN# | Cache Enable. |
| LOCK# | Bus Lock. Indicates that the current bus cycle is locked. |
| M/IO# | Memory Input-Output. Primary bus cycle definition pin. |
| NA# | Next Address. Indicates external memory system is ready to accept a new bus cycle. |
| NMI/LINT1 | Non-Mask able Interrupt. If APIC is enabled, this becomes LINT1. |
| PCD | Page Cache Disable. |
| PCHK# | Parity Check. |
| PEN# | Parity Enable. |
| PM0 - PM1 | Performance Monitoring pins. Can also act as BreakPoint pins BP0 and BP1. |
| PRDY | Probe Ready. |
| PWT | Page Write Through. |
| R/S# | Run/Stop. Places processor in an idle state. |
| RESET | Reset. |
| SCYC | Split Cycle. |
| SMI# | System Management Interrupt. Allows processor to enter System Management Mode. |
| SMIACT# | System Management Interrupt Active. Indicates that processor is in System Management Mode. |
| STPCLK# | Stop Clock. Stops internal clock of processor causing core to consume less power. |
| TCK | Testability Clock. Used to clock state information and data into and out of the processor during boundary scan. |
| TDI | Test Data Input. Serial input for the test logic. |
| TDO | Test Data Output. Serial output for the test logic. |
| TMS | Test Mode Select. |
| TRST# | Test Reset. |
| Vcc2DET | Vcc2 Detect. Identifies processor that require a lower core voltage. |
| W/R# | Write/Read. Primary bus cycle definition pin. |
| WB/WT# | Write Back/Write Through. Allows data cache to be defined as write-back or write-through. |
AMD Specific Pin Designations
| KEY | Key pin. Non-functional pin to prevent CPU insertion into a Socket 5 motherboard. |
| Vcc2H/L# | Identifies core voltage of the K6 processor (model 7, 8, and 9 chips). AMD states: "Upon sampling VCC2DET Low to identify dual-voltage processor requirements, system logic should sample Vcc2H/L# to identify the core voltage requirements for 2.9v and 3.2v products (High) and 2.2v products (Low)." |
La informacion original fue encontrada aqui http://users.erols.com/chare/486pin.htm (este link esta roto).
